372 search results - page 28 / 75 » On the Fault Testing for Reversible Circuits |
FPL
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
EURODAC
1995
IEEE
14 years 5 days ago
1995
IEEE
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
DSD
2005
IEEE
13 years 10 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper, we propose a new circuit transformation technique in conjunction with the use of a special diagnostic test pattern, named SO-SLAT pattern, to achieve higher multipl...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...