372 search results - page 57 / 75 » On the Fault Testing for Reversible Circuits |
ET
2002
13 years 7 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
IOLTS
2002
IEEE
14 years 12 days ago
2002
IEEE
The reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reco...
CF
2004
ACM
14 years 28 days ago
2004
ACM
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...