372 search results - page 64 / 75 » On the Fault Testing for Reversible Circuits |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...
ATS
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method an...
VTS
2000
IEEE
13 years 12 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...