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» On the Fault Testing for Reversible Circuits
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ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 11 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
VTS
2008
IEEE
119views Hardware» more  VTS 2008»
14 years 1 months ago
Error Sequence Analysis
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
Jaekwang Lee, Intaik Park, Edward J. McCluskey
FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
13 years 11 months ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
CONSTRAINTS
2007
112views more  CONSTRAINTS 2007»
13 years 7 months ago
Maxx: Test Pattern Optimisation with Local Search Over an Extended Logic
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
Francisco Azevedo
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
14 years 12 days ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi