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» On the energy-efficiency of speculative hardware
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MICRO
2002
IEEE
159views Hardware» more  MICRO 2002»
14 years 1 months ago
Master/slave speculative parallelization
Master/Slave Speculative Parallelization (MSSP) is an execution paradigm for improving the execution rate of sequential programs by parallelizing them speculatively for execution ...
Craig B. Zilles, Gurindar S. Sohi
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 6 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
SBACPAD
2007
IEEE
129views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Md. Mafijul Islam
ISCA
2003
IEEE
89views Hardware» more  ISCA 2003»
14 years 2 months ago
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences
A majority of the papers published in leading computer architecture conferences use SPEC CPU2000, or its predecessor SPEC CPU95, which has become the de facto standard for measuri...
Daniel Citron
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
14 years 1 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...