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» On the energy-efficiency of speculative hardware
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IPPS
1994
IEEE
13 years 11 months ago
Building Multithreaded Architectures with Off-the-Shelf Microprocessors
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
Herbert H. J. Hum, Kevin B. Theobald, Guang R. Gao
MICRO
1994
IEEE
123views Hardware» more  MICRO 1994»
13 years 11 months ago
The effects of predicated execution on branch prediction
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
Gary S. Tyson
ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
13 years 11 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
TAP
2010
Springer
134views Hardware» more  TAP 2010»
13 years 5 months ago
Testing First-Order Logic Axioms in Program Verification
Program verification systems based on automated theorem provers rely on user-provided axioms in order to verify domain-specific properties of code. However, formulating axioms corr...
Ki Yung Ahn, Ewen Denney