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» On two-step routing for FPGAS
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FPL
2006
Springer
115views Hardware» more  FPL 2006»
13 years 11 months ago
A Congestion Driven Placement Algorithm for FPGA Synthesis
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
Yue Zhuo, Hao Li, Saraju P. Mohanty
TVLSI
2008
106views more  TVLSI 2008»
13 years 7 months ago
New Non-Volatile Memory Structures for FPGA Architectures
A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
David Choi, Kyu Choi, John D. Villasenor
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
13 years 5 months ago
A PUF design for secure FPGA-based embedded systems
The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counterpiracy...
Jason Helge Anderson
FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
14 years 28 days ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose
FPL
2010
Springer
124views Hardware» more  FPL 2010»
13 years 5 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson