170 search results - page 29 / 34 » On two-step routing for FPGAS |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
—Valiant’s concept of Randomized Load Balancing (RLB), also promoted under the name ‘two-phase routing’, has previously been shown to provide a cost-effective way of implem...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
FPGA
2004
ACM
14 years 24 days ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...