34 search results - page 1 / 7 » On-chip high performance signaling using passive compensatio... |
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
ICCD
2008
IEEE
14 years 3 months ago
2008
IEEE
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
TC
2008
13 years 6 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
CAL
2008
13 years 7 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...