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MAM
2011
349views Communications» more  MAM 2011»
13 years 3 months ago
An iterative logarithmic multiplier
The paper presents a new multiplier enabling achievement of an arbitrary accuracy. It follows the same idea of number representation as the Mitchell’s algorithm, but does not use...
Zdenka Babic, Aleksej Avramovic, Patricio Bulic
ISSS
1995
IEEE
117views Hardware» more  ISSS 1995»
14 years 2 days ago
Scheduling and resource binding for low power
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
Enric Musoll, Jordi Cortadella
ASPDAC
2010
ACM
183views Hardware» more  ASPDAC 2010»
13 years 6 months ago
Multi-operand adder synthesis on FPGAs using generalized parallel counters
Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypro...
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
ICCD
2006
IEEE
132views Hardware» more  ICCD 2006»
14 years 5 months ago
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
Osama Al-Khaleel, Christos A. Papachristou, Franci...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 5 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh