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» Optimal Clock Period for Synthesized Data Paths
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TCAD
1998
83views more  TCAD 1998»
13 years 8 months ago
Telescopic units: a new paradigm for performance optimization of VLSI designs
—This paper introduces a novel optimization paradigm for increasing the throughput of digital systems. The basic idea consists of transforming fixed-latency units into variable-...
Luca Benini, Enrico Macii, Massimo Poncino, Giovan...
WEBDB
2001
Springer
113views Database» more  WEBDB 2001»
14 years 1 months ago
Indexing XML Data with ToXin
Indexing schemes for semistructured data have been developed in recent years to optimize path query processing by summarizing path information. However, most of these schemes can ...
Flavio Rizzolo, Alberto O. Mendelzon
ASPDAC
2009
ACM
212views Hardware» more  ASPDAC 2009»
14 years 3 months ago
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
Kwangok Jeong, Andrew B. Kahng
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 5 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
14 years 27 days ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha