261 search results - page 20 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ICCAD
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper presents an approach to reduce interconnect cost by insertion of identity operations in a CDFG. Other than previous approaches, it is based on systematic pattern analys...
ASPDAC
2004
ACM
14 years 14 days ago
2004
ACM
Abstract - We propose an integrated archltectural/physicdplanning approach named priority assignment optimization to mioimize the current surge in high performance power eifkient c...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes a novel architecture synthesis algorithm for single-loop single-bit ∆Σ modulators. We defined a generic modulator architecture and derived its noise and si...
ITC
1993
IEEE
14 years 25 days ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
ITC
2002
IEEE
14 years 1 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...