261 search results - page 8 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
ITC
2000
IEEE
13 years 12 months ago
2000
IEEE
In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson ...
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
VTS
2000
IEEE
13 years 12 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
— Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships ...