38 search results - page 4 / 8 » Optimal Transistor Tapering for High-Speed CMOS Circuits |
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
DAC
1997
ACM
14 years 23 days ago
1997
ACM
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
ISLPED
1999
ACM
14 years 27 days ago
1999
ACM
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
ISPD
1999
ACM
14 years 27 days ago
1999
ACM
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...