102 search results - page 10 / 21 » Optimal gradient clock synchronization in dynamic networks |
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
ISPD
1999
ACM
13 years 12 months ago
1999
ACM
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
EAAI
2008
13 years 7 months ago
2008
This paper presents the design of an infinite horizon nonlinear optimal neurocontroller that replaces the conventional automatic voltage regulator and the turbine governor (CONVC)...
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...