378 search results - page 3 / 76 » Optimal integrated code generation for VLIW architectures |
LCTRTS
2005
Springer
14 years 25 days ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
CASES
2003
ACM
14 years 17 days ago
2003
ACM
Code size has always been an important issue for all embedded applications as well as larger systems. Code compression techniques have been devised as a way of battling bloated co...
DATE
2002
IEEE
14 years 9 days ago
2002
IEEE
Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s sys...
ICCD
1999
IEEE
13 years 11 months ago
1999
IEEE
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...