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ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
14 years 2 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
ICNP
2009
IEEE
14 years 2 months ago
ESC: Energy Synchronized Communication in Sustainable Sensor Networks
—With advances in energy harvesting techniques, it is now feasible to build sustainable sensor networks (SSN) to support long-term applications. Unlike battery-powered sensor net...
Yu Gu, Ting Zhu, Tian He
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
BROADNETS
2007
IEEE
14 years 2 months ago
Resource dimensioning in WDM networks under state-based routing schemes
— Network dimensioning for wavelength-routed WDM networks has been extensively studied to maximize connection acceptance rate while minimizing the total cost. However, Internet s...
Xiaolan J. Zhang, Sun-il Kim, Steven S. Lumetta
VTC
2007
IEEE
161views Communications» more  VTC 2007»
14 years 2 months ago
Early Results on Hydra: A Flexible MAC/PHY Multihop Testbed
— Hydra is a flexible wireless network testbed being developed at UT Austin. Our focus is networks that support multiple wireless hops and where the network, especially the MAC,...
Ketan Mandke, Soon-Hyeok Choi, Gibeom Kim, Robert ...