158 search results - page 2 / 32 » Optimality and Stability Study of Timing-Driven Placement Al... |
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in m...
ISPD
2009
ACM
14 years 1 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
DAC
2003
ACM
14 years 8 days ago
2003
ACM
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
ISPD
1999
ACM
13 years 11 months ago
1999
ACM
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
ICCAD
1995
IEEE
13 years 10 months ago
1995
IEEE
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...