66 search results - page 3 / 14 » Optimization of critical paths in circuits with level-sensit... |
ICCAD
2000
IEEE
14 years 6 hour ago
2000
IEEE
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...