92 search results - page 4 / 19 » Optimization of shield structures in analog integrated circu... |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
ICCAD
2000
IEEE
14 years 19 hour ago
2000
IEEE
In this paper, we present a novel approach to use test stimuli generated by digital components of a mixed-signal circuit for testing its analog components. A wavelet transform is ...
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
Abstract—This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultr...
ISQED
2000
IEEE
2000
IEEE
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
14 years 4 hour ago
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
SBCCI
2006
ACM
14 years 1 months ago
2006
ACM
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...