— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
We present a discrete simulation model for software projects which explicitly takes a scheduling strategy as input. The model represents varying staff skill levels, component coup...