1912 search results - page 261 / 383 » Optimizing interconnection policies |
191
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ICES
2010
Springer
15 years 2 months ago
2010
Springer
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
189
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SIGOPS
2010
14 years 11 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
152
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DAC
2002
ACM
16 years 5 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
134
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ICCAD
2002
IEEE
16 years 1 months ago
2002
IEEE
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...
178
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GLVLSI
2009
IEEE
15 years 11 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...