2703 search results - page 131 / 541 » Optimizing memory transactions |
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper, we give an overview of the trade-off to improve yield and optimize silicon manufacturing cost. The specific technology focus is on large embedded memories in comple...
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
PARA
2004
Springer
14 years 2 months ago
2004
Springer
Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
ICCD
2008
IEEE
14 years 5 months ago
2008
IEEE
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...