Sciweavers

2048 search results - page 315 / 410
» Optimizing pipelines for power and performance
Sort
View
DAC
1999
ACM
14 years 9 days ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
CLUSTER
2007
IEEE
13 years 12 months ago
A feasibility analysis of power-awareness and energy minimization in modern interconnects for high-performance computing
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...
Reza Zamani, Ahmad Afsahi, Ying Qian, V. Carl Hama...
DAC
2010
ACM
13 years 12 months ago
Networks on Chips: from research to products
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address th...
Giovanni De Micheli, Ciprian Seiculescu, Srinivasa...
CASES
2005
ACM
13 years 10 months ago
Automating custom-precision function evaluation for embedded processors
Due to resource and power constraints, embedded processors often cannot afford dedicated floating-point units. For instance, the IBM PowerPC processor embedded in Xilinx Virtex-...
Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne ...
ESANN
2000
13 years 9 months ago
Load forecasting dealing with medium voltage network reconfiguration
Planing the operation in modern power systems requires suitable anticipation of load evolution at different levels of distribution network. Under this perspective, load forecasting...
José Nuno Fidalgo, João Abel Pe&cced...