954 search results - page 56 / 191 » Optimizing power and performance for reliable on-chip networ... |
ICC
2009
IEEE
14 years 2 months ago
2009
IEEE
— In this paper, a distributed power control algorithm is proposed for wireless relay networks in interference-limited environments. The objective is to minimize the total transm...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
ISPD
2005
ACM
14 years 1 months ago
2005
ACM
With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We pe...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
The placement of on-die decoupling capacitors (decap) between the power and ground supply grids has become a common practice in high performance processor designs. In this paper, ...