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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 22 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
SAC
2009
ACM
14 years 2 months ago
Impact of NVRAM write cache for file system metadata on I/O performance in embedded systems
File systems make use of part of DRAM as the buffer cache to enhance its performance in traditional systems. In this paper, we consider the use of Non-Volatile RAM (NVRAM) as a w...
In Hwan Doh, Hyo J. Lee, Young Je Moon, Eunsam Kim...
LCTRTS
2005
Springer
14 years 1 months ago
Generation of permutations for SIMD processors
Short vector (SIMD) instructions are useful in signal processing, multimedia, and scientific applications. They offer higher performance, lower energy consumption, and better res...
Alexei Kudriavtsev, Peter M. Kogge
DAC
2003
ACM
14 years 27 days ago
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
13 years 11 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...