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» Overview on Low Power SoC Design Technology
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ISCAS
2003
IEEE
156views Hardware» more  ISCAS 2003»
14 years 28 days ago
GNOMES: a testbed for low power heterogeneous wireless sensor networks
Continuing trends in sensor, semiconductor and communication systems technology (smaller, faster, cheaper) make feasible very dense networks of fixed and mobile wireless devices ...
Erik Welsh, Walt Fish, J. Patrick Frantz
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 1 months ago
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design
UML is gaining increased attention as a system design language, as indicated by current standardization activities such as the SysML initiative and the UML for SoC Forum. Moreover...
Yves Vanderperren, Wim Dehaene
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
14 years 1 days ago
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, ...
ISLPED
2007
ACM
94views Hardware» more  ISLPED 2007»
13 years 9 months ago
Design of an efficient power delivery network in an soc to enable dynamic power management
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
Behnam Amelifard, Massoud Pedram