We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx’s Virtex-5 FPGAs. An iterative “basic” module outputs a 32 bit col...
This paper presents a DES/3DES core that will support Cipher Block Chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virte...
This paper presents the results of applying an attack against the Data Encryption Standard (DES) implemented in some applications, using side-channel information based on CPU delay...
This paper presents a variety of plaintext-recovering attacks against SSH. We implemented a proof of concept of our attacks against OpenSSH, where we can verifiably recover 14 bi...
Martin R. Albrecht, Kenneth G. Paterson, Gaven J. ...
Matsui’s one-dimensional Alg. 2 can be used for recovering bits of the last round key of a block cipher. In this paper a truly multidimensional extension of Alg. 2 based on estab...