Sciweavers

5424 search results - page 1047 / 1085
» Parallel Computing with FPGAs - Concepts and Applications
Sort
View
DAC
2008
ACM
14 years 9 months ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel
SI3D
2010
ACM
14 years 3 months ago
Fast capacity constrained Voronoi tessellation
Lloyd relaxation is widely employed to generate point distribution for a variety of applications in computer graphics, computer vision, and image processing. However, Lloyd relaxa...
Hongwei Li, Diego Nehab, Li-Yi Weiy, Pedro V. Sand...
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
14 years 3 months ago
A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
NOCS
2009
IEEE
14 years 3 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 3 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy
« Prev « First page 1047 / 1085 Last » Next »