Sciweavers

2563 search results - page 511 / 513
» Parallel matrix algorithms and applications
Sort
View
FOCS
1992
IEEE
14 years 2 months ago
On the Fault Tolerance of Some Popular Bounded-Degree Networks
In this paper, we analyze the fault tolerance of several bounded-degree networks that are commonly used for parallel computation. Among other things, we show that an N-node butterf...
Frank Thomson Leighton, Bruce M. Maggs, Ramesh K. ...
DAC
2010
ACM
14 years 2 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
14 years 2 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
14 years 2 months ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
VISSYM
2007
14 years 1 months ago
A Tri-Space Visualization Interface for Analyzing Time-Varying Multivariate Volume Data
The dataset generated by a large-scale numerical simulation may include thousands of timesteps and hundreds of variables describing different aspects of the modeled physical pheno...
Hiroshi Akiba, Kwan-Liu Ma