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» Parallel simulation of chip-multiprocessor architectures
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VIS
2007
IEEE
149views Visualization» more  VIS 2007»
14 years 9 months ago
Time Dependent Processing in a Parallel Pipeline Architecture
Pipeline architectures provide a versatile and efficient mechanism for constructing visualizations, and they have been implemented in numerous libraries and applications over the p...
John Biddiscombe, Berk Geveci, Ken Martin, Kenn...
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 3 months ago
Exploring parallelizations of applications for MPSoC platforms using MPA
—This paper presents a tool for exploring different parallelization options for an application. It can be used to quickly find a high-quality match between an application and a ...
Rogier Baert, Erik Brockmeyer, Sven Wuytack, Thoma...
EUROPAR
2006
Springer
14 years 5 days ago
Supporting Reconfigurable Parallel Multimedia Applications
Abstract. Programming multimedia applications for System-on-Chip (SoC) architectures is difficult because streaming communication, user event handling, reconfiguration, and paralle...
Maik Nijhuis, Herbert Bos, Henri E. Bal
DAC
2010
ACM
13 years 8 months ago
RAMP gold: an FPGA-based architecture simulator for multiprocessors
We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throu...
Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yun...
HPCA
2003
IEEE
14 years 8 months ago
Variability in Architectural Simulations of Multi-Threaded Workloads
Multi-threaded commercial workloads implement many important internet services. Consequently, these workloads are increasingly used to evaluate the performance of uniprocessor and...
Alaa R. Alameldeen, David A. Wood