770 search results - page 4 / 154 » Parallel simulation of chip-multiprocessor architectures |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
VLDB
2005
ACM
14 years 25 days ago
2005
ACM
With the advent of chip multiprocessors, exploiting intra-transaction parallelism is an attractive way of improving transaction performance. However, exploiting intra-transaction ...
ASPLOS
1996
ACM
13 years 11 months ago
1996
ACM
Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we l...