149 search results - page 20 / 30 » Parametric Fault Simulation and Test Vector Generation |
VLSID
1996
IEEE
13 years 11 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
TVLSI
2008
13 years 7 months ago
2008
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
ATS
2003
IEEE
14 years 20 days ago
2003
IEEE
Abstract: As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates th...