8 search results - page 1 / 2 » Parasitic capacitance modeling for multilevel interconnects |
APCCAS
2002
IEEE
14 years 1 months ago
2002
IEEE
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for dr...
TVLSI
2002
13 years 8 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
ICCAD
1996
IEEE
14 years 20 days ago
1996
IEEE
-- In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due toincreasing operating...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....