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» Patching Processor Design Errors
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ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
14 years 1 months ago
Energy/Power Estimation of Regular Processor Arrays
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
Sanjay V. Rajopadhye, Steven Derrien
SIGGRAPH
1996
ACM
14 years 23 days ago
Automatic Reconstruction of B-Spline Surfaces of Arbitrary Topological Type
Creating freeform surfaces is a challenging task even with advanced geometric modeling systems. Laser range scanners offer a promising alternative for model acquisition--the 3D sc...
Matthias Eck, Hugues Hoppe
EMSOFT
2005
Springer
14 years 2 months ago
Compiler-guided register reliability improvement against soft errors
With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely ...
Jun Yan, Wei Zhang
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 3 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
PLDI
2006
ACM
14 years 2 months ago
Practical dynamic software updating for C
Software updates typically require stopping and restarting an application, but many systems cannot afford to halt service, or would prefer not to. Dynamic software updating (DSU) ...
Iulian Neamtiu, Michael W. Hicks, Gareth Stoyle, M...