112 search results - page 10 / 23 » Path based buffer insertion |
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
—Load-balanced switches have received a great deal of attention recently as they are much more scalable than other existing switch architectures in the literature. However, as th...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
FPGA
2001
ACM
14 years 3 days ago
2001
ACM
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
ISCAS
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper presents a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both sorting and p...