29 search results - page 4 / 6 » Path delay test compaction with process variation tolerance |
MEMOCODE
2007
IEEE
14 years 1 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we...