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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 23 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
WOSP
2004
ACM
14 years 1 months ago
Experimenting different software architectures performance techniques: a case study
In this paper we describe our experience in performance analysis of the software architecture of the NICE case study which is responsible for providing several secure communicatio...
Simonetta Balsamo, Moreno Marzolla, Antinisca Di M...
SC
2004
ACM
14 years 1 months ago
A Performance and Scalability Analysis of the BlueGene/L Architecture
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
Kei Davis, Adolfy Hoisie, Greg Johnson, Darren J. ...
ASPDAC
2004
ACM
98views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Enabling on-chip diversity through architectural communication design
- In this paper, we explore a new concept, called on-chip diversity, and introduce a design methodology for such emerging systems. Simply speaking, on-chip diversity means mixing d...
Tudor Dumitras, Sam Kerner, Radu Marculescu
CODES
2006
IEEE
14 years 1 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst