114 search results - page 14 / 23 » Performance Evaluation of Task Pools Based on Hardware Synch... |
ISSS
2002
IEEE
14 years 18 days ago
2002
IEEE
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
WH
2010
13 years 2 months ago
2010
Body Sensor Networks (BSNs) consist of sensor nodes deployed on the human body for health monitoring. Each sensor node is implemented by interfacing a physiological sensor with a ...
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...