618 search results - page 3 / 124 » Performance and energy optimization of concurrent pipelined ... |
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
ICCAD
1993
IEEE
1993
IEEE
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
13 years 11 months ago
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the m...
DATE
2003
IEEE
14 years 26 days ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...