Sciweavers

157 search results - page 16 / 32
» Performance area efficiency in chip multiprocessors with mic...
Sort
View
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
14 years 2 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 1 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 2 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
SBACPAD
2007
IEEE
91views Hardware» more  SBACPAD 2007»
14 years 2 months ago
Impacts of Multiprocessor Configurations on Workloads in Bioinformatics
Bioinformatics is among the most active research areas in computer science. In this study, we investigate a suite of workloads in bioinformatics on two multiprocessor systems with...
Youfeng Wu, Mauricio Breternitz Jr., Victor Ying
CSC
2010
13 years 6 months ago
An Evaluation of Parallel Knapsack Algorithms on Multicore Architectures
Emergence of chip multiprocessor systems has dramatically increased the performance potential of computer systems. Since the amount of exploited parallelism is directly influenced ...
Hammad Rashid, Clara Novoa, Apan Qasem