157 search results - page 4 / 32 » Performance area efficiency in chip multiprocessors with mic... |
TC
2008
13 years 7 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energ...
ISCA
2010
IEEE
13 years 6 months ago
2010
IEEE
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...