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JSA
2010
158views more  JSA 2010»
13 years 2 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
TCAD
2008
183views more  TCAD 2008»
13 years 7 months ago
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
Abstract--For modern embedded systems in the realm of highthroughput multimedia, imaging, and signal processing, the complexity of embedded applications has reached a point where t...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
IEEEARES
2006
IEEE
14 years 1 months ago
Secure Enhanced Wireless Transfer Protocol
When IEEE 802.11i draft[1] proposed TKIP, it is expected to improve WEP on both active and passive attack methods. TKIP uses more sophisticated methods to distribute and manage se...
Jin-Cherng Lin, Yu-Hsin Kao, Chen-Wei Yang
VISUALIZATION
2005
IEEE
14 years 1 months ago
Dataset Traversal with Motion-Controlled Transfer Functions
In this paper, we describe a methodology and implementation for interactive dataset traversal using motion-controlled transfer functions. Dataset traversal here refers to the proc...
Carlos D. Correa, Deborah Silver
ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
14 years 4 months ago
Architectural Support for Run-Time Validation of Control Flow Transfer
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
Yixin Shi, Sean Dempsey, Gyungho Lee