54 search results - page 11 / 11 » Performance-complexity analysis in hardware-software codesig... |
CODES
2005
IEEE
14 years 17 days ago
2005
IEEE
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
CODES
2003
IEEE
14 years 8 days ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
CODES
2005
IEEE
14 years 17 days ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...