192 search results - page 24 / 39 » Pipelined FPGA Adders |
FPL
2003
Springer
14 years 1 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
FPL
2007
Springer
13 years 12 months ago
2007
Springer
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
ESANN
2006
13 years 9 months ago
2006
Abstract. Despite several previous studies, little progress has been made in building successful neural systems for image segmentation in digital hardware. Spiking neural networks ...
RECONFIG
2008
IEEE
14 years 2 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
FPL
2003
Springer
14 years 1 months ago
2003
Springer
Local search methods such as WSAT have proven to be successful for solving SAT problems. In this paper, we propose two host-FPGA (Field Programmable Gate Array) co-implementations,...