192 search results - page 36 / 39 » Pipelined FPGA Adders |
ESTIMEDIA
2004
Springer
14 years 1 months ago
2004
Springer
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
FPL
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
DATE
2000
IEEE
14 years 12 days ago
2000
IEEE
Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are t...
MICRO
1999
IEEE
14 years 8 days ago
1999
IEEE
This study compares the speed, area, and power of di erent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processo...
CHES
2003
Springer
13 years 11 months ago
2003
Springer
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...