351 search results - page 34 / 71 » Plug-and-Play Architectural Design and Verification |
DAC
1994
ACM
14 years 1 months ago
1994
ACM
-- In previous work, Hu and Dill identified a common cause of BDD-size blowup in high-level design verification and proposed the method of implicitly conjoined invariants to addres...
BIRTHDAY
2006
Springer
14 years 1 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
DAC
2006
ACM
14 years 3 months ago
2006
ACM
VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder...
DAC
2011
ACM
12 years 9 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...