142 search results - page 4 / 29 » Polymorphic On-Chip Networks |
ASAP
2007
IEEE
13 years 9 months ago
2007
IEEE
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
DATE
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
SIPS
2008
IEEE
14 years 2 months ago
2008
IEEE
Intellectual Properties (IPs) mapping algorithms for On-Chip-Networks (OCNs) allocate a set of IPs onto given network topologies. The existing mapping algorithms limit a single IP...
ICCAD
2000
IEEE
14 years 21 hour ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
CAL
2008
13 years 7 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...