51 search results - page 3 / 11 » Post-Layout Optimization for Deep Submicron Design |
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
As the technology migrates into the deep submicron manufacturing (DSM) era, the critical dimension of the circuits is getting smaller than the lithographic wavelength. The unavoid...
ISLPED
2000
ACM
13 years 12 months ago
2000
ACM
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
ISQED
2002
IEEE
14 years 16 days ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...