51 search results - page 4 / 11 » Post-Layout Optimization for Deep Submicron Design |
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
TCAD
1998
13 years 7 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...